Electronic Design

Could This “2D” Transistor Process Transform Logic and Power Device Production?

CDimension’s technology, which enables semiconductor makers to manufacture arrays of extremely small, fast, and efficient “2D” transistors, has the potential to change what’s possible for both digital ...
EDN

LDMOS process aims to boost power transistors

London – Royal Philips Electronics is using a 0.6-micron laterally diffused MOS technology in a range of power transistors it plans to start sampling this year. The first device to be introduced using ...
Business Wire

X-FAB Expands CMOS Optical Sensors Portfolio with Industry’s First 4-Transistor Image Sensor Process for High-Speed Applications Requiring Large Pixels

ERFURT, Germany--(BUSINESS WIRE)--X-FAB Silicon Foundries, the leading More-than-Moore foundry, today introduced XS018, the first specialized 0.18µm CMOS process for fast and large image sensor pixels ...
Design-Reuse

A Review Paper on CMOS, SOI and FinFET Technology

In 1958, the first integrated circuit flip-flop was built using two transistors at Texas Instruments. The chips of today contain more than 1 billion transistors. The memory that could once support an ...
Semiconductor Engineering

A Benchmark Study Of Complementary-Field Effect Transistor (CFET) Process Integration Options: Comparing Bulk vs. SOI vs. DSOI Starting Substrates

Compare 3 process flows in terms of robustness to process variation to see which one has the lowest likelihood of processing failures. Sub-5 nm logic nodes will require an extremely high level of ...
Business Wire

Search For The Next: UK Collaboration Unveils Bizen® a Transistor Wafer Process Technology Promising to Slash Lead Times, Wafer Area and Process Layers While Increasing Speed ...

NOTTINGHAM, England--(BUSINESS WIRE)--A UK collaboration between Nottingham-based start-up, Search For The Next (SFN) and Glenrothes-based Semefab may be set to disrupt the semiconductor industry by ...
Semiconductor Engineering

A Benchmark Study Of Complementary-Field Effect Transistor (CFET) Process Integration Options

Sub-5 nm logic nodes will require an extremely high level of innovation to overcome the inherent real-estate limitations at this increased device density. One approach to increasing device density is ...